#Synplify pro name layer0 generator

Good practice in RTL would suggest that this would be at the lowest level of hierarchy of the SoC design but in the prototype, a wrapper adds levels below the logic already in place in the SoC. The diagram in Figure 88 shows the basic arrangement, in this case two wrappers used in the same level of hierarchy. Experienced prototypers will be very familiar with wrappers and may indeed have built up their own libraries of wrappers for use in various situations. Using memory wrappersДЄ wrapper is a small piece of RTL that contains an item to be implemented in the FPGA, but which has a top-level boundary that maps to the component/module instantiation in the SoC RTL. We call these adapters вЂњwrappersвЂќ and we shall spend some time exploring their use next. We can do this without changing the existing RTL, but instead we add extra RTL files to act as an adaptor between the black-box RAM instantiations in the SoC RTL and the necessary FPGA or external equivalent. When mapping SoC RAMs it is necessary to adapt the RTL so that the FPGA tool flow can map it into the appropriate resource. FPGAs have the ability to interface through fast IO to external memories and even built-in support for interfacing to standard external RAMs, such as DDR2 and DDR3. Furthermore, most SoC designs contain much larger RAMs than a few Megabytes, so for these reasons it will probably be necessary to map some of the SoC memory to external RAM components on the boards. Interfaces to external RAM: FPGAs have a growing amount of internal RAM but it is inefficient to use up whole FPGAs just to map a few Megabytes of RAM from an ASIC.

In any case, if the size of the RAM is small (e.g., 16x8, 36x2) then distributed RAMs are generally a better choice than BlockRAM. In cases where the SoC RAM topology is not compatible with BlockRAM (e.g., quad-port or bit-addressable RAM) then distributed RAMs can be used.

With the use of surrounding logic, there is great flexibility in how distributed RAM can be used.

Distributed RAM: The look-up tables in the FPGA can also be configured as RAM and because these are spread throughout the device, we call them distributed RAMs.

#Synplify pro name layer0 generator

Furthermore, embedded dual-port or single-port RAM modules, ROM modules, synchronous FIFOs, and data width converters are easily implemented from BlockRAMs using the XilinxВ® CORE Generatorв„ў module generator tool.

The BlockRAMs may be configured as single-port, simple dual-port and true dual-port.

During a write operation the memory can be set to have the data output either remain unchanged, reflect the new data being written or the previous data now being overwritten. The memory content can be initialized or cleared by the configuration bitstream so that contents are already present when the device comes out of reset. Each port can be configured in one of the available widths, independent of the other port. The two ports are symmetrical and totally independent, sharing only the stored data.

Write and read are synchronous operations.

Each 18Kb BlockRAM can be configured as a 16K x 1, 8K x2, 4K x 4, 2K x 9, or 1K x 18 memory. they can also be cascaded to create a 64Kx1 RAM. Each 36-Kbit BlockRAM can be configured in a number of ways e.g., 32K x 1, 16K x 2 etc.

BlockRAM: The VirtexВ®-6 block RAM stores up to 36K bits of data and can be configured as either two independent 18-Kbit RAMs, or one 36- Kbit RAM.

In FPGAs, there are two different groups of RAMS Block RAMs and distributed RAMs.

Before exploring that further, here is a quick recap on FPGA RAMs (more details are in chapter 3). In addition, there are limits imposed by the memory architectures available in the FPGA device itself, so there is no guarantee that all types of SoC RAMs can be directly mapped into BlockRAMs or distributed RAMs that are supported in the FPGA device. FPGA tools donвЂ™t understand any instantiated RAMs used in the SoC design.